1. Field of the Invention
The present invention relates generally to voltage-to-frequency converters. More particularly, the present invention is directed towards a novel charge balance voltage-to-frequency converter utilizing CMOS circuity to provide a digital pulse output proportional to an analog voltage input signal.
2. Description of Related Art
Voltage-to-frequency converters are well known. Broadly, a voltage-to-frequency converter produces an output frequency proportional to the level of an input signal. Voltage-to-frequency converters have been implemented using a variety of technologies, including transistor-to-transistor logic (TTL) and complementary metal oxide structure (CMOS). Charge balancing in such converters is desirable because the integrating capacitor's tolerance does not affect the accuracy of the conversion.
One example of a conventional voltage-to-frequency converter is the integrating section of a device produced by Scientific Columbus, of Columbus, Ohio, designated SC-60 Watt/Watthour Standard, which produces an output pulse train whose frequency is proportional to the power level of an input signal. The voltage level and the current level of the input signal are modulated to produce a signal whose pulse width and pulse amplitude are varied in proportion to the average power level of the input signal. This modulated signal is applied to the input of an integrator. Also applied to this input is a gated negative current source signal whose duration is controlled by the output signal from a quartz crystal referenced monostable multivibrator. The gated signal from the current source is added to the modulated signal at the input of the integrator. The output from the integrator is applied to a first input of a comparator, whose second input is connected to a voltage reference source. This circuit requires the use of a dual polarity power supply. The output of the comparator, which is a high repetition rate pulse train whose rate is accurately proportional to the power level of the input signal, is provided to the input of a divider and to the input of the quartz crystal referenced monostable multivibrator. The divider provides driving pulses at a desired rate to isolated open-collector output stages.
Another conventional voltage-to-frequency converter is a device designated 8700 CMOS A/D Converter, produced by Teledyne Corporation, of Hawthorne, Calif. This monolithic integrated circuit chip performs A/D conversion utilizing CMOS circuitry to provide a charge balancing of the output of an integrating amplifier. The input signal to the circuit is fed to the inverting terminal of an integrating amplifier. The output of the integrating amplifier is compared by a comparator to a threshold voltage generated by an internal clock and control logic. The output of the comparator, in combination with an internal clock, generated by the internal clock and control logic, controls a switch used to gate a reference voltage, V.sub.REF, which is applied to the inverting input of the integrating amplifier to provide the charge balancing of the amplifier output. The application of the reference voltage to the inverting input necessitates the use of a dual polarity power supply. The output of the internal clock and control logic is applied to data counters, whose output is supplied, via a bus, to output latches. These stages accumulate the number of V.sub.REF pulses required to charge balance the output of the integrating amplifier over a predetermined time interval.
While the Teledyne circuit is superior in some respects to the charge balancing techniques previously discussed, it has its own deficiencies. For example, it requires separate comparator, switch, internal clock and control logic, data counter and output latch stages. Its output is limited to a binary word based on a given conversion period. Therefore, the output of the circuit is only applicable to a limited number of applications where the conversion period of the circuit corresponds to the sample period desired. It also requires a dual polarity power supply. Additionally, since the clock controlling the feedback pulses and the data acquisition are internal, the conversion period cannot be varied to optimally suit a given application.